ZTE

ZTE Communications ›› 2012, Vol. 10 ›› Issue (1): 63-70.

• Research Paper • Previous Articles    

A Histogram-Based Static Error Correction Technique for Flash ADCs: Implementation

J Jacob Wikner1, Armin Jalili2, Sayed Masoud Sayedi2, and Rasoul Dehghani2   

  1. 1. Department of Electrical Engineering, Link?ping University, SE-581 83 Link?ping, Sweden;
    2. Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan 84156-83111, Iran
  • Online:2012-03-25 Published:2012-03-25
  • About author:J. Jacob Wikner (jacob.wikner@liu.se) received his PhD from the Department of Electrical Engineering, Link?ping University, Sweden, in 2001. He has worked as research engineer at Ericsson Microelectronics, senior analog design engineer at Infineon Technologies, and senior design engineer and chip architect at Sicon Semiconductor. Dr. Wikner has been an associate professor at Link?ping University since 2009. His research interests include biologically inspired architectures, high-speed A/D and D/A converters, and general analog and mixed-signal design. He holds six patents, has published 40 scientific papers, and has co-authored“CMOS Data Converters for Telecommunication.”He is the co-founder of CogniCatus and AnaCatum Design.

    Armin Jalili (arminj@ec.iut.ac.ir) received his BSc and MSc degrees in electrical engineering from Isfahan University of Technology (IUT) in 2004 and 2006. He is currently working towards his PhD degree in electrical engineering at IUT. His interests include ADC design.

    Sayed Masoud Sayedi (m_sayedi@cc.iut.ac.ir) received his BSc and MSc degrees in electrical engineering from Isfahan University of Technology (IUT), Iran, in 1986 and 1988. He received his PhD degree in electronics from Concordia University in 1996. From 1988 to 1992, and since 1997, he has worked at IUT, where he is currently an associate professor in the Department of Electrical and Computer Engineering. His research interests include VLSI fabrication processes, low power VLSI circuits, vision sensors, and data converters.

    Rasoul Dehghani (dehghani@cc.iut.ac.ir ) received his BSEE, MSc, and PhD degrees in electrical engineering from Sharif University of Technology (SUT), Iran, in 1988, 1991 and 2004. From 1987 to 1991, he worked on design and implementation of different electronic circuits and systems at SUT. From 1991 to 1998, he was involved in implementing various electronic circuits focused on industrial applications. From 1998 to 2004, he worked with Emad Co. in Tehran and Jaalaa Company in Kuala Lumpur as a senior design engineer. Since 2006, he has been an assistant professor at IUT. His research interests include RF IC design for wireless communication, frequency synthesis, and low-voltage low-power circuits.

PDF (PC)

Abstract: In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, high-speed flash analog-to-digital converters (ADCs). In [1], we theoretically describ the calibration technique and perform a behavioral-level simulation to test its functionality [1]. In this work, we discuss some issues in transistor-level implementation. The predominant factors that contribute to static errors such as reference generator mismatch and track-and-hold (T/H) gain error can be treated as input-referred offsets of each comparator. Using the proposed calibration technique, these errors can be calibrated with minimal detriment to the dynamic performance of the converter. We simulate a transistor-level implementation of a 5-bit, 1 GHz ADC in a 1.2 V, 65 nm CMOS process. The results show that DNL can be improved from 2.5 LSB to below 0.7 LSB after calibration, and INL can be improved from 1.6 LSB to below 0.6 LSB after calibration.

Key words: Calibration, chopping, flash ADC, PDF generator, reference generator circuit, track and hold circuit