ZTE

ZTE Communications ›› 2011, Vol. 9 ›› Issue (4): 3-9.

• Special Topic • Previous Articles     Next Articles

Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

Mehmood Awan1, Yannick Le Moullec1, Peter Koch1, and Fred Harris2   

  1. 1. Technology Platforms Section, Dept. of Electronic Systems, Aalborg University, Denmark;
    2. Dept. of Electrical & Computer Engineering, San Diego State University, CA, USA
  • Online:2011-12-25 Published:2011-12-25
  • About author:Mehmood Awan (mura@es.aau.dk) received his MSc degree in electronic engineering with specialization in applied signal processing and implementation from Aalborg University in 2007. He was a research assistant for one year and started his Ph.D. in resource-optimal SDR front-ends in 2008. His research interests include multirate signal processing, SDR, hardware architectures, and embedded systems.

    Yannick Le Moullec (ylm@es.aau.dk) received his Ph.D. degree in electrical engineering from Université de Bretagne Sud, Lorient, France, in 2003. From 2003 to 2005, he was a post-doctoral fellow at the Center for Embedded Software Systems, Aalborg University, Denmark. From 2005 to 2008, he was an assistant professor at the Department of Electronic Systems, Aalborg University, where he is now an associate professor. His research interests include methods and tools for HW/SW co-design, embedded systems, and reconfigurable computing.

    Peter Koch (pk@es.aau.dk) received his M.Sc. and Ph.D. degrees in Electrical Engineering from Aalborg University, Denmark, in 1989 and 1996. Since 1997, he has been an associate professor at the Department of Electronic Systems, Aalborg University, working in the interdisciplinary field between DSP and resource-optimal real-time architectures. From 2006 to 2010, he headed the Center for Software Defined Radio, Aalborg University. His research interests include optimization between DSP algorithms and architectures, and low-energy HW/SW design.

    Fred Harris (fred.harris@sdsu.edu) holds the Signal Processing Chair of the Communication Systems and Signal Processing Institute at San Diego State University where he teaches DSP and communication systems. He holds 20 patents for digital receivers, and he lectures around the world on DSP applications. He is an adjunct of the Princeton IDA-CCR Center for Communications Research and is the author of“Multirate Signal Processing for Communication systems.”

PDF (PC)

Abstract: This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N-path polyphase filter. Such a system allows resampling by arbitrary ratios while performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. This resampling technique is based on sliding cyclic data load interacting with cyclic-shifted coefficients. A non-maximally-decimated polyphase filter bank (where the number of data loads is not equal to the number of M subfilters) processes M subfilters in a time period that is less than or greater than the M data loads. A polyphase filter bank with five different resampling modes is used as a case study for embedded resampling in SDR front-ends. These modes are (i) maximally decimated, (ii) under-decimated, (iii) over-decimated, and combined up- and down-sampling with (iv) single stride length, and (v) multiple stride lengths. These modes can be used to obtain any required rational sampling rate change in an SDR front-end based on a polyphase channelizer. They can also be used for translation to and from arbitrary center frequencies that are unrelated to the output sample rates.

Key words: SDR, digital front-ends, polyphase filter bank, embedded resampling