VFabric: A Digital Twin Emulator for Core Switching Equipment

doi:10.12142/ZTECOM.202501012

ZTE Communications ›› 2025, Vol. 23 ›› Issue (1): 90-100.DOI: 10.12142/ZTECOM.202501012

• Research Papers • Previous Articles Next Articles

VFabric: A Digital Twin Emulator for Core Switching Equipment

WANG Qianglin¹, ZHANG Xiaoning¹(), YANG Yi¹, FAN Chenyu¹, YUE Yangyang², WU Wei², DUAN Wei²

^1.School of Information and Communication Engineering, University of Electronic Science and Technology of China, Chengdu 610000, China
^2.ZTE Corporation, Shenzhen 518057, China

Received:2023-10-24 Online:2025-03-25 Published:2025-03-25
About author:WANG Qianglin received his MS degree in electronic information from University of Electronic Science and Technology of China in 2024. He joined Alibaba Corporation in 2024 and is now a network engineer there.
ZHANG Xiaoning ( xnzhang@uestc.edu.cn) received his MS and PhD degrees in electronic information from the School of Communication and Information Engineering, University of Electronic Science and Technology of China (UESTC) in 2005 and 2007, respectively. Since 2007, he has been a professor with UESTC. His current research interests include software-defined networking and virtualization of network functions.
YANG Yi received his MS degree in electronic information from University of Electronic Science and Technology of China in 2024. He joined Tianyi Cloud Corporation in 2024.
FAN Chenyu received her MS degree in electronic information from University of Electronic Science and Technology of China in 2024. She joined EricssonCloud Corporation in 2024.
YUE Yangyang is a senior engineer at ZTE Corporation. She is engaged in application software development for wired communications.
WU Wei is an engineer at ZTE Corporation. He is engaged in application software development for wired communications. His primary research focuses on large-scale router penetration testing, performance simulation, and functional development.
DUAN Wei is a senior R&D chief engineer at ZTE Corporation. He is engaged in the key technology research of IP networks and intelligent computing center networks. He has applied for more than 30 patents.
Supported by:
the National Natural Science Foundation of China (NSFC)(62171085);the ZTE Industry?University?Institute Cooperation Funds(HC?CN-20220722010)

Abstract

Abstract:

The proliferation of heterogeneous networks, such as the Internet of Things (IoT), unmanned aerial vehicle (UAV) networks, and edge networks, has increased the complexity of network operation and administration, driving the emergence of digital twin networks (DTNs) that create digital-physical network mappings. While DTNs enable performance analysis through emulation testbeds, current research focuses on network-level systems, neglecting equipment-level emulation of critical components like core switches and routers. To address this issue, we propose vFabric (short for virtual switch), a digital twin emulator for high-capacity core switching equipment. This solution implements virtual switching and network processor (NP) chip models through specialized processes, deployable on single or distributed servers via socket communication. The vFabric emulator can realize the accurate emulation for the core switching equipment with 720 ports and 100 Gbit/s per port on the largest scale. To our knowledge, this represents the first digital twin emulation framework specifically designed for large-capacity core switching equipment in communication networks.

Key words: digital twin network, core switch/router, sockets, network emulation

WANG Qianglin, ZHANG Xiaoning, YANG Yi, FAN Chenyu, YUE Yangyang, WU Wei, DUAN Wei. VFabric: A Digital Twin Emulator for Core Switching Equipment[J]. ZTE Communications, 2025, 23(1): 90-100.

Figures/Tables 13

Figure 1 Architecture of digital twin network

Figure 2 Logic model of large-capacity switching equipment

Figure 3 Framework of the digital twin model

Figure 4 Framework of the process chip

Figure 5 Framework of the producer-consumer model

Figure 6 Framework of the synchronization module

Figure 7 Schematic diagrams of online and offline processes

Figure 8 Flow charts of synchronization

Figure 9 Flow charts of exception handling

Table 1 Proportion of packets of different lengths

Packet Length/B	Weight
64	449
130	160
260	200
577	80
1 518	110
9 000	1

Table 2 Number of packets forwarded by different chips

Type of Device	Number of Packets
Port	400 000
NP	8 000 000
Switch	9 000 000
Total server	28 800 000

Figure 10 Simulation time of different synchronization algorithms

Figure 11 Change of the packet loss rate with time

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VFabric: A Digital Twin Emulator for Core Switching Equipment

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