ZTE

ZTE Communications ›› 2012, Vol. 10 ›› Issue (1): 54-62.

• Research Paper • Previous Articles     Next Articles

Hardware Architecture of Polyphase Filter Banks Performing Embedded Resampling for Software-Defined Radio Front-Ends

Mehmood Awan1, Yannick Le Moullec1, Peter Koch1, and Fred Harris2   

  1. 1. Technology Platforms Section, Dept. of Electronic Systems, Aalborg University, Denmark;
    2. Dept. of Electrical & Computer Engineering, San Diego State University, CA, USA
  • Received:2011-09-20 Online:2012-03-25 Published:2012-03-25
  • About author:Mehmood Awan (mura@es.aau.dk) received his MSc degree in electronic engineering with specialization in applied signal processing and implementation from Aalborg University in 2007. He was a research assistant for one year and started his PhD in resource-optimal SDR front-ends in 2008. His research interests include multirate signal processing, SDR, hardware architectures, and embedded systems.

    Yannick Le Moullec (ylm@es.aau.dk) received his PhD degree in electrical engineering from Université de Bretagne Sud, Lorient, France, in 2003. From 2003 to 2005, he was a post-doctoral fellow at the Center for Embedded Software Systems, Aalborg University, Denmark. From 2005 to 2008, he was an assistant professor at the Department of Electronic Systems, Aalborg University, where he is now an associate professor. His research interests include methods and tools for HW/SW co-design, embedded systems, and reconfigurable computing.

    Peter Koch (pk@es.aau.dk) received his MSc and PhD degrees in Electrical Engineering from Aalborg University, Denmark, in 1989 and 1996. Since 1997, he has been an associate professor at the Department of Electronic Systems, Aalborg University, working in the interdisciplinary field between DSP and resource-optimal real-time architectures. From 2006 to 2010, he headed the Center for Software Defined Radio, Aalborg University. His research interests include optimization between DSP algorithms and architectures, and low-energy HW/SW design.

    Fred Harris (fred.harris@sdsu.edu) holds the Signal Processing Chair of the Communication Systems and Signal Processing Institute at San Diego State University where he teaches DSP and communication systems. He holds 20 patents for digital receivers, and he lectures around the world on DSP applications. He is an adjunct of the Princeton IDA-CCR Center for Communications Research and is the author of“Multirate Signal Processing for Communication systems.”

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Abstract: In this paper, we describe resource-efficient hardware architectures for software-defined radio (SDR) front-ends. These architectures are made efficient by using a polyphase channelizer that performs arbitrary sample rate changes, frequency selection, and bandwidth control. We discuss area, time, and power optimization for field programmable gate array (FPGA) based architectures in anM -path polyphase filter bank with modifiedN -path polyphase filter. Such systems allow resampling by arbitrary ratios while simultaneously performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. A non-maximally decimated polyphase filter bank, where the number of data loads is not equal to the number ofM subfilters, processesM subfilters in a time period that is either less than or greater than theM data-load’s time period. We present a load-process architecture (LPA) and a runtime architecture (RA) (based on serial polyphase structure) which have different scheduling. In LPA,N subfilters are loaded, and thenM subfilters are processed at a clock rate that is a multiple of the input data rate. This is necessary to meet the output time constraint of the down-sampled data. In RA,M subfilters processes are efficiently scheduled withinN data-load time while simultaneously loadingN subfilters. This requires reduced clock rates compared with LPA, and potentially less power is consumed. A polyphase filter bank that uses different resampling factors for maximally decimated, under-decimated, over-decimated, and combined up- and down-sampled scenarios is used as a case study, and an analysis of area, time, and power for their FPGA architectures is given. For resource-optimized SDR front-ends, RA is superior for reducing operating clock rates and dynamic power consumption. RA is also superior for reducing area resources, except when indices are pre-stored in LUTs.

Key words: SDR, FPGA, Digital Front-ends, Polyphase Filter Bank, Embedded Resampling