In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, high-speed flash analog-to-digital converters (ADCs). In [1], we theoretically describ the calibration technique and perform a behavioral-level simulation to test its functionality [1]. In this work, we discuss some issues in transistor-level implementation. The predominant factors that contribute to static errors such as reference generator mismatch and track-and-hold (T/H) gain error can be treated as input-referred offsets of each comparator. Using the proposed calibration technique, these errors can be calibrated with minimal detriment to the dynamic performance of the converter. We simulate a transistor-level implementation of a 5-bit, 1 GHz ADC in a 1.2 V, 65 nm CMOS process. The results show that DNL can be improved from 2.5 LSB to below 0.7 LSB after calibration, and INL can be improved from 1.6 LSB to below 0.6 LSB after calibration.

High-speed, high-accuracy data converters are attractive for use in most RF applications. Such converters allow direct conversion to occur between the digital baseband and the antenna. However, high speed and high accuracy make the analog components in a converter more complex, and this complexity causes more power to be dissipated than if a traditional approach were taken. A static calibration technique for flash analog-to-digital converters (ADCs) is discussed in this paper. The calibration is based on histogram test methods, and equivalent errors in the flash ADC comparators are estimated in the digital domain without any significant changes being made to the ADC comparators. In the trimming process, reference voltages are adjusted to compensate for static errors. Behavioral-level simulations of a moderate-resolution 8-bit flash ADC show that, for typical errors, ADC performance is considerably improved by the proposed technique. As a result of calibration, the differential nonlinearities (DNLs) are reduced on average from 4 LSB to 0.5 LSB, and the integral nonlinearities (INLs) are reduced on average from 4.2 LSB to 0.35 LSB. Implementation issues for this proposed technique are discussed in our subsequent paper,“A Histogram-Based Static-Error Correction Technique for Flash ADCs: Implementation Aspects.”