Design of Raptor-Like LDPC Codes and High Throughput Decoder Towards 100 Gbit/s Throughput

doi:10.12142/ZTECOM.202303012

ZTE Communications ›› 2023, Vol. 21 ›› Issue (3): 86-92.DOI: 10.12142/ZTECOM.202303012

收稿日期:2023-01-29 出版日期:2023-09-21 发布日期:2023-09-21

Design of Raptor-Like LDPC Codes and High Throughput Decoder Towards 100 Gbit/s Throughput

LI Hanwen, BI Ningjing, SHA Jin()

School of Electronic Science & Engineering, Nanjing University, Nanjing 210000, China

Received:2023-01-29 Online:2023-09-21 Published:2023-09-21
About author:LI Hanwen received his BS degree from Fuzhou University, China in 2020, and MS degree from Nanjing University, China in 2023. His research interests include very-large scale integration design for digital signal processing and error control coding.|BI Ningjing received her BS degree and MS degree in electrical engineering from Nanjing University, China, in 2020 and 2023, respectively. Her research interest focuses on digital very-large scale integration design.|SHA Jin (shajin@nju.edu.cn) received his BS degree in physics and PhD degree in electrical engineering from Nanjing University, China in 2002 and 2007, respectively. From 2012 to 2013, he was a visiting professor with Stanford University, USA. He is currently an associate professor with School of Electronic Science and Engineering, Nanjing University. His current research interests include very-large scale integration design for digital signal processing, error control coding, flash memory error control, and heterogeneous computing systems.
Supported by:
ZTE Industry-University-Institute Cooperation funds(2020ZTE01-03)

摘要/Abstract

Abstract:

This paper proposes a raptor-like low-density parity-check (RL-LDPC) code design together with the corresponding decoder hardware architecture aiming at next-generation mobile communication. A new kind of protograph different from the 5G new radio (NR) LDPC basic matrix is presented, and a code construction algorithm is proposed to improve the error-correcting performance. A multi-core layered decoder architecture that supports up to 100 Gbit/s throughput is designed based on the special protograph structure.

Key words: RL-LDPC, error floor, high throughput, protograph, 5G NR

. [J]. ZTE Communications, 2023, 21(3): 86-92.

LI Hanwen, BI Ningjing, SHA Jin. Design of Raptor-Like LDPC Codes and High Throughput Decoder Towards 100 Gbit/s Throughput[J]. ZTE Communications, 2023, 21(3): 86-92.

图/表 8

Figure 1 Tanner graph

Figure 2 Structure of raptor-like low-density parity-check (RL-LDPC) code

Figure 3 Construction constraint structure

Figure 4 Multi-core decoder architecture

Figure 5 Decoder core architecture

Figure 6 Performance comparison after optimizing the number of 6-cycle

Figure 7 Performance comparison under rate of 8/9

Table 1 Implementation results

Resources	Implementation in Ref. [15]	Proposed
LUTs	1 015 935	861 574
FFs	62 460	62 460
Brams	66	66

参考文献 15

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Design of Raptor-Like LDPC Codes and High Throughput Decoder Towards 100 Gbit/s Throughput

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